file:下载器连接开发板图示.jpg file:使用前读我.txt file:感谢信.JPG file:XSpirit_V1原理图.pdf file:FPGA毕业设计精选.zip file:夏宇闻-Verilog经典教程.pdf file:深入浅出玩转FPGA 第二版.pdf file:例说FPGA:可直接用于工程项目的第一手经验.pdf file:边练边学—快速入门 Verilog vhdl.pdf file:FPGA设计 实战演练(逻辑篇).pdf file:仿真测试激励文件(testbench)编写方法.pdf file:超声波测距资料(HC-SR04).zip file:JR6001语音模块-资料包.zip file:HC-05主从机一体蓝牙模块资料.zip file:串口调试助手.rar file:Xilinx下载器驱动安装.pdf file:Xilinx.ISE.Design.Suite.14.6.rar file:modelsim_se_10.1a_emouse.rar file:ISE14.6软件安装.pdf file:Guagle.exe file:debussy-nt.zip file:CADENCE16.6.rar file:VGA_J3.rar file:LCD1602.rar file:JTD_J3.zip file:Board_Test.rar file:Interface.brd file:16 为什么Verilog能支持大型设计.7z file:15 Verilog模块的种类和用途.7z file:14 FPGA设计中时序逻辑设计要点.7z file:12 FPGA中数字系统的构成.7z file:10 Verilog中reg和wire的不同点.7z file:07 modelsim和quartus的使用.7z file:ADDA原理图.pdf file:ADDA模块顶层.JPG